A phase synchronizing circuit comprising a phase locked loop (PLL) is often used for generating a high-speed clock inside a logic LSI, adjusting phase with a RAM module connected to the outside of an LSI. The circuit configuration of the PLL is stated in detail, for example, in “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessor” by I. Young (IEEE Journal of Solid-state Circuits, Vol. SC-27, pp. 1599-1607, November 1992) etc.
The basic configuration of the PLL is shown in FIG. 1. The PLL is composed of a phase comparator (PFD) 1, a charge pump (CP) 2, a loop filter (LF) 3, a voltage controlled oscillator (VCO) 4, and a divider (DV) 5. The phase comparator 1 detects a phase difference between a reference signal Fr inputted into one terminal thereof and a feedback signal Fb inputted into the other terminal thereof, and outputs pulse signals UP, DN that depend on the phase difference between the two inputs. The charge pump 2 drives the loop filter 3 according to the signals UP, DN. The loop filter 3 smoothes an output of the charge pump 2 and outputs a control voltage V1f to the VCO 4. The VCO 4 oscillates at a frequency that depends on the control voltage V1f. Between an output terminal of the VCO 4 and the other terminal into which the feedback signal Fb to the phase comparator 1 is inputted, the divider 5 is provided to constitute a feedback loop.
By adopting such a configuration, the PLL is controlled such that the phase and frequency of the reference signal Fr agree with those of the feedback signal Fb. Here, an arbitrary positive integer can be chosen as a frequency division number N of the divider 5, and the frequency of the signal Fo outputted from the VCO 4 becomes N times that of the reference signal at the time of PLL convergence.
If the above-mentioned PLL circuit is loaded in an LSI as a device for generating a clock, it is desired that the PLL can operate at various frequencies according to different settings, such as a high frequency operation while the LSI carries out processing, and a low frequency operation while being standing by. Therefore, the PLL is expected to be capable of operating in a wide frequency range.
Further, if the PLL is applied to phase adjustment of clocks inside/outside the LSI, the PLL is similarly required to be capable of operating in a wide frequency range because the operating frequency of an external bus varies broadly according to user's target performance.
In order for the PLL to operate in such a wide frequency range as in these cases, the VCO 4 is required to oscillate in the whole target frequency range. However, characteristics of the VCO 4 may vary according to process variations when the PLL is constructed on a semiconductor substrate and also according to environmental variations. If this variation range is large, there may be a case where the VCO 4 cannot satisfy a predetermined frequency range with the same design. Conventionally, the VCO 4 is provided with a function of adjusting oscillation characteristics in conjunction with a calibration technology applied thereto to automatically adjusts the frequency range such that the VCO 4 satisfies a desired oscillation frequency range. Such a technology is disclosed in, for example, JP-A-49597/2000. Hereafter, this conventional PLL is described as an example.
A configuration of the conventional PLL having a calibration circuit is shown in FIG. 2. The configuration with the phase comparator (PFD) 11, the charge pump (CP) 2, the loop filter (LF) 3, and the divider (DV) 5 is the same as that of FIG. 1. The voltage controlled oscillator (VCO) is composed of a gm cell 6 for converting voltage to current and a current controlled oscillator (ICO) 7. Furthermore, this PLL is provided with a calibration control circuit (CC) 8 for optimizing currents flowing in the VCO 4.
An example of the calibration control circuit 8 is shown in FIG. 3. The calibration control circuit 8 has a monitor circuit (MON) 9 for receiving the output signals UP, DN from the phase comparator 1 and, based on monitored values of these, for generating data used for adjusting current flowing in the gm cell 6 and the ICO 7. According to the data generated by this monitor circuit 9, current values of the gm cell 6 and the ICO 7 are adjusted thereby varying the frequency of the VCO 4.
That is, the calibration control circuit 8 writes data defining currents to flow in the gm cell 6 and the ICO 7 in a data register (DRG) 11 (FIG. 3) from the monitor circuit 8 through a serial interface (SIF) 10 and changes the number of connection of constituent current sources in current source banks 12, 13 which are connected to the gm cell and the ICO 7, respectively, by means of outputs of a data register 11.
Next, a calibration operation of the VCO 4 that uses the above-mentioned circuit is explained referring to FIG. 2 and FIG. 3.
The calibration is performed by first setting the PLL to be an open loop and then repeating both a lower limit setting (wherein a frequency at a lower limit value of the control voltage is measured, and the VCO 4 is adjusted until the frequency becomes not higher than a predetermined frequency) and an upper limit setting (wherein a frequency at an upper limit value of the control voltage is measured, and the VCO 4 is adjusted until the frequency becomes not lower than a predetermined frequency) until the VCO 4 satisfies the predetermined oscillation frequency range.
In the lower limit and the upper limit settings, the frequency is determined using the signals UP, DN of the phase comparator 1. During the lower limit decision, the reference signal Fr is set at the lower limit, the control voltage V1f of the VCO 4 is set at the lower limit, and the signals UP, DN are monitored for a period of M cycles such that whether or not the frequency of the VCO 4 satisfies the predetermined frequency range is determined. If the lower limit frequency does not satisfy the predetermined lower limit value, the numbers of the addition of the current source banks 12, 13 are reduced, and the lower limit decision is conducted again. If the lower limit frequency satisfies the predetermined lower limit value, the processing moves to the upper limit decision.
During the upper limit decision, the reference signal Fr is set at the upper limit and the control voltage V1f of the VCO 4 is set at the upper limit such that the frequency decision is conducted as in the lower limit decision. If the upper limit frequency does not satisfy the predetermined upper limit value, the numbers of the addition of the current source banks 12, 13 are increased, and the upper limit decision is conducted again. If the upper limit frequency satisfies the predetermined upper limit value, the flow moves to the lower limit decision.
By repeating the above-mentioned upper limit and lower limit decision operations, the VCO 4 is adjusted so as to satisfy the predetermined frequency range.
In the conventional example described above, if the voltage controlled oscillator operates at a low voltage, it is necessary to use low threshold transistors that were miniaturized. Such a low-voltage operation causes a problem that variations in threshold, temperature, supply voltage, etc. influence a frequency control characteristic significantly thereby further increasing a leak current.
FIG. 4 shows a simulation example of the VCO 4 at a supply voltage of 0.7 V. When the threshold value is set to −0.05 V, the supply voltage varies +0.15 V, and the threshold variation varies at +0.15 V due to variations of a manufacture process, and a temperature variation ranges from −40 degrees C. to 125 degrees C. Here, a characteristic line MX of the simulation results under a maximum leak-current condition and a characteristic line MN of the results under a minimum velocity condition, i.e., a lowest frequency condition, are shown in FIG. 4.
In FIG. 4, even if the VCO 4 is designed such that the oscillation frequency thereof satisfies the frequency range of 50-200 MHz under the minimum velocity condition, when the VCO comes to be under the maximum leak current condition (giving the lowest threshold value) due to variations in the manufacture process, the leak current is large and a controllable lowest frequency extends to 100 MHz at most. If the VCO 4 with such characteristics is used for the PLL operating at 50 MHz to 200 MHz, there occurs a problem that the PLL cannot cover the range between 50 MHz and 100 MHz when the VCO 4 comes under the maximum leak-current condition due to the variations in the manufacture process.
When the frequency of the VCO 4 is adjusted by the prior art, the oscillation frequency due to the leak current cannot be reduced because the VCO 4 is adjusted solely by the adjustment of a current source size, and there has not been considered existence of a condition in which the calibration cannot be conducted normally as mentioned above.
Further, in the prior art, the frequency decision is done by monitoring the signals UP, DN of the phase comparator 2 which requires a long measurement cycle for comparing total pulses because structurally neither of the signal UP or the signal DN is outputted continuously so as to lengthen the calibration time. This is presented in “Monolithic Phase-locked Loops and Clock Recovery Circuits” by B. Razavi (IEEE PRESS).
Thus, it is the object of the present invention to provide a phase synchronizing circuit capable of automatically adjusting a voltage controlled oscillator (VCO) such that the VCO satisfies a predetermined frequency range even if the VCO is oscillated by the leak current.
Further, it is another object of the present invention to provide a phase synchronizing circuit capable of performing frequency setting of the VCO at high speed.